1. Field of the Invention
This invention relates to a semiconductor memory element, more particularly to a method for fabricating a semiconductor memory element having excellent insulation property suitable for high density integration.
2. Description of the Related Art
A conventional semiconductor memory element having a stacked capacitor cell is fabricated through forming the stacked capacitor cell by successive stacking of storage electrodes, dielectric films, and plate electrodes on a silicon substrate having switching transistors formed thereon, and forming a bit line, finally.
FIG. 1 is a section of the conventional semiconductor memory element.
Referring to FIG. 1, the conventional semiconductor memory cell includes a semiconductor substrate 10, and switching transistors, stacked capacitors, and a bit line 21, formed on the substrate.
Each of the switching transistors has a gate insulation film 11 and gate 12 formed on the substrate 10, and impurity regions 13 for source/drain formed in the substrate 10 on both sides of the gate. Each of the stacked capacitors has a storage electrode 17 and a plate electrode 19 formed over the impurity region of the switching transistor, with a dielectric film 18 formed between the storage electrode 17 and the plate electrode 19.
The bit line 21 is formed over the impurity region 13 of the switching transistor between adjacent stacked capacitors, and an insulation film 20 is formed for insulating between the bit line 21 and the plate electrodes 19 of the stacked capacitors.
One each of a plug 15 is formed both between the storage electrode 17 of the stacked capacitor and the impurity region under the storage electrode 17 and between the bit line 21 and the impurity region 13 of the switching transistor under the bit line 21, and one each of an insulation film 14 or 16 is formed of insulating both between the gate 12 and the plug 15 and between the plug 15 and the storage electrode 17.
FIGS. 2A-2F show process steps for fabricating the conventional semiconductor memory element of FIG. 1.
First, as shown in FIG. 2A, switching transistors are formed on a semiconductor substrate 10. That is, gate insulation films 11 and gates 12 are formed on the substrate 10, and impurity regions 13 for sources/drains are formed in the substrate 10 on both sides of each gate by injecting impurity ions thereto. Then, insulation films 14 are formed on the surface thereof excluding the impurity regions 13.
As shown in FIG. 2B, plugs 15 are formed by depositing a continuous layer of conductive material and subjecting it to patterning to leave the material on the surface of the impurity regions 13, and as shown in FIG. 2C, insulation films 16 are formed on portions of the surfaces of the plugs 15.
As shown in FIG. 2D, each of the stacked capacitors is formed by successive forming of a storage electrode 17 which makes contact with the impurity region through the plug 15, a dielectric film 18, and a plate electrode 19 as shown in FIG. 2E, a bit line contact 22 is formed by forming an insulation film 20 and removing the insulation film 20 over the plug 15 between the stacked capacitors. Finally, the bit line 21 is formed on the insulation film 20 to make contact with the exposed plug 15 through the bit line contact 22 to complete the conventional semiconductor memory cell as shown in FIG. 2F.
In the foregoing semiconductor memory element, the distance between the bit line 21 and the plate electrodes 19 of the capacitors insulated by the insulation film 20 becomes reduced as the semiconductor memory elements are highly integrated. Therefore, in case of misalignment during the formation of the bit line contact as the distances between the bit line and the plate electrodes of the stacked capacitors become smaller, with the insulation film 20 between them being thinner, there has arisen a problem of reduced insulation property. In case the misalignment is serious, shorts can happen between the plate electrodes and the bit line.
SUMMARY OF THE INVENTION
An object of the present invention is to resolve the foregoing problem of the conventional art by providing a method for fabricating a semiconductor memory element, having an improved insulation property between a plate electrode of a capacitor and a bit line by forming a self-aligning plate electrode of the capacitor.
Another object of the present invention is a method for fabricating a semiconductor memory element having excellent insulation properties suitable for high density integration.
These and other objects and features of the present invention are achieved by a method for fabricating a semiconductor memory element comprising the steps of the successive formation of gate insulation films and gates on a substrate forming impurity regions in the substrate on both sides of each of the gates by injecting impurity ions thereto, forming a first insulation film on the surface thereof, forming storage electrode contacts to the impurity regions on one side of each of the gates and an underside protection layer on the impurity region on the other side of each of the gates by subjecting the first insulation film to etching to expose the impurity regions on one side of each of the gates, forming a plurality of layered storage electrodes each making contact to the impurity region through the contact, forming a plurality of layered sacrificing layers on each of the storage electrodes, forming sacrificing sidewall spacers at sidewalls of each of the storage electrodes and the sacrificing layers, forming a second insulation film over the entire surface thereof, forming an upperside protection layer on the underside protection layer and exposing the sacrificing layers by subjecting the second insulation layers to etching, exposing the storage electrodes by etching the exposed sacrificing layers and subsequently etching the sacrificing sidewall spacers, forming a dielectric film on each of the exposed storage electrodes, and forming a self-aligned plate electrode on each of the dielectric films by etching the dielectric film to a depth sufficient to expose the upperside protection layer.